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Trojan Tolerant Hardware & Supply Chain Security

Vasilios MavroudisDan Cvrcek

Proposes an architecture for building trusted, backdoor-tolerant hardware security modules out of untrusted commercial off-the-shelf components.

Summary

Supply Chain Vulnerabilities in Silicon Fabrication

High-assurance security systems traditionally operate on the assumption that underlying hardware components are trustworthy. Vasilios Mavroudis and Dan Cvrcek challenge this foundational model, highlighting that modern integrated circuit fabrication is almost universally outsourced to overseas foundries where covert hardware Trojans or subtle manufacturing defects can be introduced without detection by standard post-fabrication tests.

Limitations of Hardware Verification

Traditional quality assurance and optical inspection techniques are incapable of reliably detecting stealthy hardware Trojans that activate only under rare clock conditions or subtle analogue environmental triggers. Because comprehensive destructive silicon forensics is economically infeasible for commercial deployments, organizations require an architectural approach to hardware trust that tolerates compromised components.

Architecting Backdoor Tolerant Security Modules

The authors introduce a high-assurance hardware architecture capable of surviving the compromise of individual integrated circuits. They present a proof-of-concept backdoor-tolerant Hardware Security Module (HSM) constructed entirely from low-cost, off-the-shelf commercial components. The design incorporates component diversification, threshold cryptography, and independent non-overlapping supply chains to ensure that no single vendor or foundry can unilaterally compromise system keys.

Enforcing Mutual Distrust Between Components

The core operational principle of the architecture is mutual distrust: critical cryptographic operations and random number generation are split across isolated heterogeneous microcontrollers that cross-verify outputs before signing or decrypting payloads. Benchmarks demonstrate that this multi-chip consensus model incurs minimal performance overhead while providing rigorous fault tolerance and confidentiality guarantees against malicious silicon modifications.

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